Chameleon: A Multiplier-Free Temporal Convolutional Network Accelerator for End-to-End Few-Shot and Continual Learning from Sequential Data
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Mar 5, 2026 - Python
Chameleon: A Multiplier-Free Temporal Convolutional Network Accelerator for End-to-End Few-Shot and Continual Learning from Sequential Data
This is my senior project, we aim to design a Low-cost-AI-Accelerator based on Google's Tensor Processing Unit.
⚡ A seamless integration of HuggingFace Transformers & Diffusers with RBLN SDK for efficient inference on RBLN NPUs.
KV260 integration lane for PCCX™ v002 LLM IP-core bring-up, validation, and board/runtime evidence.
PyTorch extension for Rebellions NPU
PCCX™ specification, documentation, and ecosystem coordination hub for open AI accelerator IP.
Pytorch implementation of TRAM: Training Approximate Multiplier Structures for Low-Power AI Accelerators
Rapid prototyping framework for deploying and evaluating ML models on hardware
NPU soft IP, designed for true parallel execution on the edge.
T1C — Open-Source AI Accelerator Architecture. Like RISC-V did for CPUs, T1C does for AI chips. Fully open source, MIT Licensed.
Quiet the fan on Tenstorrent Blackhole PCIe accelerators under Windows. Minimal KMDF driver that sends ARC ASIC_STATE0 on D0Entry.
Curated Edge AI resources for computer vision & audio: hardware, frameworks, benchmarks, literature, and communities (excluding mobile).
The Hyze IPU (Intelligence Processing Unit) is a revolutionary hardware-software co-design project aimed at redefining the efficiency and security of AI inference. Unlike traditional GPU-centric architectures, the Hyze IPU leverages a heterogeneous computing model that seamlessly integrates CPU, GPU, and a custom-built IPU into a single, AI chip
This project implements AXI-based matrix multiply accelerator.
INT8 Systolic-Array AI Accelerator on Zynq SoC with HW-SW Co-Design and Roofline Performance Analysis
A complete RISC-V SoC in SystemVerilog: pipelined CPU + memory-mapped systolic-array NPU accelerator, running real firmware that offloads a matrix multiply. Includes a small RV32I assembler. Self-checking testbench + CI.
FORCE AI: Fast Optimization for Resource-Constrained Efficient AI Inference
A Kubernetes Device Plugin for Hailo AI accelerators, enabling seamless scheduling of AI inference workloads on edge devices like the Raspberry Pi AI HAT+.
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