CMOS XnOR Gate design using Cadence Virtuoso including schematic design, simulation and layout verification (DRC, LVS REX).
This project presents the complete design and verification of a CMOS XNOR gate implemented using Cadence Virtuoso. The design follows a standard full-custom VLSI design flow including schematic creation, symbol generation, functional simulation, layout implementation, physical verification, and parasitic RC extraction.
The XNOR gate is an important combinational logic element widely used in digital systems for comparison operations, equality detection, and arithmetic circuits. It produces a HIGH output when both inputs are equal.
Technology : CMOS Design Tool : Cadence Virtuoso Simulation Tool : Spectre Simulator Verification : DRC, LVS Extraction : RC Parasitic Extraction Design Style : Full Custom VLSI
The Exclusive NOR (XNOR) gate is the complement of the XOR gate. It produces a HIGH output when both input signals are identical and LOW when the inputs are different.
Boolean Expression
Y = A ⊙ B
Equivalent Expression
Y = AB + A'B'
Truth Table
| A | B | Y |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
The XNOR gate therefore functions as a digital equality detector, producing HIGH output only when both inputs match.
The CMOS implementation of the XNOR gate uses complementary PMOS and NMOS transistor networks.
Pull-Up Network (PMOS)
The pull-up network connects the output to VDD when the logic condition for XNOR is satisfied.
Pull-Down Network (NMOS)
The pull-down network connects the output to ground when the XNOR condition is not satisfied.
The complementary structure ensures:
• Low static power dissipation • High noise immunity • Stable switching characteristics • Compatibility with modern CMOS fabrication technologies
The project follows the standard full-custom integrated circuit design flow used in industry.
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Logic Design Boolean expression of XNOR gate verified.
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Schematic Design Transistor level schematic implemented using CMOS transistors.
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Symbol Generation Symbol created to allow hierarchical design usage.
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Testbench Design Input stimulus signals applied to verify circuit functionality.
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Functional Simulation Transient simulation performed to observe switching behavior.
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Layout Design Physical layout implemented following CMOS layout rules.
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Design Rule Check (DRC) Verification to ensure layout follows fabrication constraints.
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Layout Versus Schematic (LVS) Verification to ensure layout connectivity matches schematic.
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Parasitic RC Extraction Resistance and capacitance values extracted from layout.
The transistor-level schematic was implemented in Cadence Virtuoso using CMOS devices to realize the XNOR Boolean logic function.
A symbol view was generated to allow the XNOR gate to be easily reused in hierarchical circuit designs.
A testbench circuit was designed to apply input stimulus signals and verify the functional behavior of the XNOR gate.
Transient simulation verifies the correct XNOR behavior. The output becomes HIGH only when both input signals are identical.
The physical layout was implemented following standard CMOS layout practices including proper transistor placement, metal routing, and well contacts.
DRC verification confirms that the layout satisfies all fabrication design rules.
LVS ensures that the connectivity of the layout matches the schematic netlist.
The LVS result confirms that the schematic and layout are electrically identical.
RC extraction identifies parasitic resistance and capacitance introduced by interconnects in the layout.
The extracted RC network is used for accurate post-layout simulation and timing analysis.
Correct XNOR logic functionality verified DRC passed successfully LVS matched successfully Parasitic RC extraction completed
Cadence Virtuoso
Abhijit Wankhede