7.PCM5102 I2S DAC
The PCM5102 board is capable of producing high-quality audio with low noise and distortion. The chosen board can be seen in Figure 1.
Figure 1: PCM5102 Audio DAC board.
The PCM5102 chip integrates a PLL (phase-locked loop) that removes the need for a master clock, simplifying the interface to a 3-wire I2S connection. It supports audio data formats from 16-bit to 32-bit with sample rates up to 384kHz.
The Board has the following pins and their functions are listed:
- VCC - Power supply (3.3V)
- GND - Ground
- FLT - Filter select (Normal latency: Low / Low latency: High)
- DMP - De-emphasis control for 44.1kHz (Off: Low / On: High)
- SCL - System clock input
- BCK - Bit clock input
- DIN - Audio data input
- LCK - Word clock input
- FMT - Audio format select (I2S: Low / Left justified: High)
- XST - Soft mute control (Mute: Low / Unmute: High)
The PCM5102 supports common audio sample rates like 8kHz, 44.1kHz, 192kHz, and even up to 384kHz with a ±4% tolerance. The audio interface uses a 3-wire serial connection (LRCK, BCK, and DIN), with BCK acting as the bit clock and LRCK as the left/right word clock. All of this can be seen in Figure 1.
Figure 1: PCM5102 specifications and modes.
The chosen I2S Audio format is given below in Figure 2, from the datasheet. The figure shows three possible audio data word lengths: 16 bits, 24 bits, and 32 bits. BCK also has different options depending on the chosen audio data word lengths.
Figure 2: PCM5102 I2S Audio format.
Connect the VCC PCM5102 pin to 3.3V, and PCM5102 GND to GND to power up the Audio DAC Board. To configure the PCM5102 Audio DAC for internal system clock generation, connect the SCL pin to GND. Additionally, it is recommended to use a ~10kΩ resistor between the XMT pin and VCC to enable soft mute control.
Inter-Integrated Circuit Sound (I2S) is a synchronous, serial communication protocol for exchanging digital audio data between sound-processing devices such as microcontrollers, audio codecs, or digital signal processors. It uses a shared clock signal to synchronize the data transmission between devices and transmits audio in a serial fashion. The protocol is often used in designs that require high-quality audio transmission. It is a serial bus interface, designed by Philip Semiconductor in February 1986 for digital audio interface between the devices.
On the physical level, the protocol requires three connections between the devices on a bus: the clock signal (SCK) for synchronizing communication partners, a word select (WS) line for switching between the left and right audio channels, and a dedicated data wire exclusively for transmitting audio information bit-by-bit. The protocol’s physical simplicity directly translates to its data format. In contrast to other protocols relying on intricate bit sequences to match particular patterns for the recipients to understand the message, I2S doesn’t rely on this approach. Instead, the clock signal continuously runs, and the bits representing the audio data are also placed continuously on the single data line. The transmission does not occur in frames of fixed sizes. Rather, the active transmitter sends any data available for transmission, while the receiver reads as many bits as possible — or as expected to be received. The only limitation is that the sender must transmit the data with the MSB first. Apart from this, the recipients and senders do not require agreement on fixed message lengths. Anything a receiver can’t process will be lost, hence why sending the MSB first is the sole requirement.
Figure 3: I2S Data Transmission.
In a typical digital audio system, data is generated for both the left and right audio channels at every sample interval. For instance, a CD-quality audio source with a sample rate of 44.1 kHz produces two 16-bit words—one for each channel—at a rate of 44,100 times per second. This results in a data rate of 1,411,200 bits per second (44,100 samples per second × 16 bits per sample × 2 channels). Such a high data rate presents a significant challenge for a single serial line to handle effectively.
A single serial data line struggles to reliably convey the word boundaries between left and right channel samples, and it also faces difficulties in extracting a clock signal without experiencing jitter. Therefore, transmitting high-fidelity audio over a simple serial line requires an improved mechanism to manage both synchronization and data integrity.
The I2S (Inter-IC Sound) protocol addresses these challenges by utilizing additional lines to carry necessary synchronization information. I2S provides a word select line (also referred to as the L/R clock), which indicates whether the data being transmitted corresponds to the left or right audio channel. Additionally, it includes a bit clock line to ensure that all components are synchronized without ambiguity or jitter. Thus, the I2S protocol consists of three main lines: a data line, a word clock line, and a bit clock line, which together facilitate reliable, high-quality audio transmission. This straightforward yet effective design of the I2S interface makes it highly suitable for digital audio applications, ensuring accurate synchronization of audio data and minimizing transmission errors, making it the preferred choice for high-quality digital-to-analog audio conversion.
Figure 4: Basic Interface Timing of I2S Bus Protocol.