This repository contains the design, verification, and automation setup for a RISC-V based processor subsystem, developed as part of an academic group project under the guidance of Dr. Amit Chavan, following industry-style workflows.
- Mr. Amit Chavan
- Alen Sojan
- Prithwin Prakash
- Ritik Kalmegh
- Shikhar Mani Tripathi
- Sidharth V Menon
- RTL design (SystemVerilog)
- Verification testcases and plans
- GitHub Issues and Project tracking
- CI-based automation
- Project documentation
- All tasks are tracked via GitHub Issues
- Progress is monitored using GitHub Projects
- Communication and updates happen via Discord
- Verification and checks are automated where feasible
For detailed workflow guidelines, labeling conventions, and repository structure, please refer to the
docs/directory.
This repository follows a strict, locked directory structure to ensure:
- Clean separation of RTL and verification
- Scalable UVM-based verification
- Easy onboarding for new contributors
- CI/CD and automation friendliness
- Industry-aligned project organization
Any deviation from this structure is not allowed without maintainer approval.
riscv-core/
├── docs/
├── rtl/
├── tb/
├── sim/
├── scripts/
└── .github/
Project documentation only.
No source code allowed.
docs/
├── architecture/
├── verification/
└── meeting_notes/
architecture/– Block diagrams, interfaces, pipeline descriptionverification/– Test plans, coverage strategy, regression flowmeeting_notes/– Guide discussions, decisions, action items
Contains only synthesizable RTL.
rtl/
├── common/
├── alu/
├── decoder/
├── regfile/
├── instr_mem/
└── top/
Rules:
- One block per directory
- No testbench or tool files
- Shared definitions go only in
common/ - Top-level integration lives in
top/
Contains all verification code, primarily UVM.
tb/
├── common/
├── alu/
├── decoder/
├── regfile/
├── instr_mem/
└── top/
Rules:
- Mirrors
rtl/one-to-one - Each block has its own environment
- Shared testbench utilities go in
common/ - Full-core verification lives in
top/
Tool-specific simulation artifacts.
sim/
├── verilator/
├── questasim/
└── vivado/
Rules:
- Simulator scripts only
- Can be freely modified
- Nothing here should be required for synthesis
Utility scripts for developers and CI.
scripts/
Examples:
- Simulation launchers
- Lint helpers
- Regression scripts
Continuous Integration helpers.
ci/
Examples:
- Verilator CI configuration
- Linting rules
- Regression hooks
GitHub-specific automation.
.github/
└── workflows/
Includes:
- CI pipelines
- Issue enforcement
- Discord notifications
The following directories are strictly locked:
rtl/tb/
Only new block subdirectories may be added. No ad-hoc restructuring is permitted.
Violations may result in PR rejection.
📌 This project emphasizes verification discipline, collaboration, and documentation, not just RTL implementation.
📌 Please adhere to all guidelines to ensure a smooth development process.