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Oluwaferanmi Arowoshola

Electrical Engineering Graduate | Embedded Systems · Firmware · FPGA · VLSI · Hardware/Software Integration

STM32 · Zephyr RTOS · Embedded Linux · FPGA · MicroBlaze · SystemVerilog · RISC-V · CMOS/VLSI · Hardware Validation

M.S. Electrical Engineering
Relocating to Dallas–Fort Worth, TX


About Me

I am an Electrical Engineering graduate focused on embedded systems, firmware, FPGA-based hardware/software integration, digital design, and semiconductor/VLSI systems.

My project work includes STM32 firmware, Zephyr RTOS experimentation, FPGA soft-core processor integration, a 5-stage pipelined RISC-V processor in SystemVerilog, full-custom CMOS VLSI design, and MOSFET fabrication process lab work.

I am currently targeting early-career roles in:

  • Embedded Systems Engineering
  • Firmware Engineering
  • Embedded Validation / Hardware Test
  • FPGA / RTL / Digital Design
  • SoC / Digital Verification
  • VLSI / Semiconductor Engineering
  • Electronics Manufacturing / Process / Test Engineering

Featured Projects

Embedded C firmware for the STM32 B-L475E-IOT01A Discovery Board that reads onboard temperature and humidity sensors and serves live environmental data through a lightweight Wi-Fi HTTP server.

Skills: STM32, Embedded C, STM32CubeIDE, Wi-Fi, HTTP server, sensor acquisition, ST-Link serial debugging


FPGA-based embedded system on the Nexys DDR board using a Xilinx MicroBlaze soft-core processor, AXI GPIO peripherals, UART, and C firmware for memory-mapped switch-to-LED hardware control.

Skills: MicroBlaze, Vivado, Vitis, FPGA, AXI GPIO, UART, embedded C, memory-mapped I/O, hardware/software integration


SystemVerilog RTL implementation of a 5-stage pipelined RISC-V processor with hazard detection, forwarding, stall/flush control, simulation verification, and Vivado synthesis.

Skills: SystemVerilog, RTL design, RISC-V, computer architecture, pipelined processor design, hazard detection, forwarding, waveform analysis


Full-custom 8-bit pipelined Vedic multiplier in 90nm CMOS with hierarchical schematic/layout design, DRC/LVS-clean verification, post-layout simulation, and 50 MHz pipelined operation.

Skills: VLSI, CMOS, Synopsys Custom Compiler, SPICE, DRC/LVS, layout design, timing analysis, physical verification


MOSFET front-end fabrication lab project covering wet oxidation, photolithography, BOE oxide etching, phosphorus diffusion, drive-in diffusion, gate oxide formation, wafer inspection, and process measurement.

Skills: IC fabrication, wafer processing, oxidation, photolithography, diffusion, Nanospec measurement, process documentation


Wireless embedded system using Zephyr RTOS on the Nordic nRF52840 platform, focused on scheduling, synchronization, device-driver interaction, BLE/Wi-Fi communication, timing behavior, and low-power embedded operation.

Skills: Zephyr RTOS, nRF52840, embedded C, BLE, task scheduling, synchronization, serial logging, real-time embedded systems


Quality management case study using inspection data, p-charts, control charts, run charts, fishbone root-cause analysis, and corrective-action planning to evaluate process stability and improvement opportunities.

Skills: Quality management, process improvement, p-charts, control charts, root-cause analysis, Excel-based data analysis, corrective-action documentation


Best-effort near real-time speech-to-speech translation system on Raspberry Pi using a multithreaded STT → translation → TTS pipeline with GUI control and performance validation.

Skills: Raspberry Pi, embedded Linux, Python, audio processing, GUI, multithreading, system integration, performance measurement


Technical Skills

Embedded Systems & Firmware

C/C++ · Python · STM32 · Zephyr RTOS · Embedded Linux · GPIO · UART · SPI · I2C · Wi-Fi · BLE · sensor integration · serial debugging

FPGA, RTL & Digital Design

SystemVerilog · Verilog · Vivado · Vitis · MicroBlaze · AXI GPIO · RISC-V · pipelined processors · computer architecture · RTL simulation · waveform analysis

VLSI & Semiconductor

CMOS circuit design · full-custom layout · Synopsys Custom Compiler · SPICE · DRC/LVS · timing analysis · IC fabrication · photolithography · oxidation · diffusion · wafer process documentation

Hardware Test & Validation

Oscilloscopes · multimeters · benchtop power supplies · soldering/basic PCB rework · hardware/software debugging · board-level validation · technical documentation

Tools

STM32CubeIDE · Vivado · Vitis · Git · MATLAB · Tera Term · Wireshark · Linux · Microsoft Excel


Education

Minnesota State University, Mankato
M.S. Electrical Engineering
B.S. Computer Engineering Technology
Undergraduate Certificate in Internet of Things


Contact

Email: feranmiarowoshola@gmail.com
LinkedIn: linkedin.com/in/oluwaferanmi-arowoshola
Resume: View Resume

Pinned Loading

  1. stm32-iot-sensor-webserver stm32-iot-sensor-webserver Public

    Embedded C firmware for STM32 B-L475E-IOT01A that reads onboard temperature/humidity sensors and serves live environmental data through a lightweight Wi-Fi HTTP server.

    C

  2. microblaze-embedded-system microblaze-embedded-system Public

    MicroBlaze FPGA embedded system on Nexys DDR using Vivado/Vitis, AXI GPIO peripherals, UART, and C firmware for memory-mapped switch-to-LED hardware control.

    C

  3. riscv-pipelined-processor riscv-pipelined-processor Public

    SystemVerilog RTL implementation of a 5-stage pipelined RISC-V processor with hazard detection, forwarding, stall/flush control, simulation verification, and Vivado synthesis.

    SystemVerilog 1

  4. vedic-multiplier-vlsi-design vedic-multiplier-vlsi-design Public

    Full-custom 8-bit pipelined Vedic multiplier in 90nm CMOS with hierarchical schematic/layout design, DRC/LVS-clean verification, post-layout simulation, and 50 MHz pipelined operation.

  5. mosfet-ic-fabrication-lab mosfet-ic-fabrication-lab Public

    MOSFET front-end fabrication lab covering oxidation, photolithography, oxide etching, phosphorus diffusion, drive-in, gate oxide formation, and process measurement.

  6. quality-management-process-improvement quality-management-process-improvement Public

    Quality management case study using inspection data, p-charts, control charts, root-cause analysis, and corrective-action planning to evaluate defect-rate improvement.