Issues · lnls-dig/bpm-gw · GitHub

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Incorrect comments in the FMC ADCs SPI interface

#110

· augustofg opened

on Oct 24, 2024

[MONIT1/MONIT tag delay] delays are applied as "ADC clock cycles" granularity

#81

· lerwys opened

on Jul 8, 2020

[FOFB sync] FOFB sync only works when switching is in "switching" mode

#80

· lerwys opened

on Jul 8, 2020

[wb_fmcpico1m_4ch] Aquisition clock must be synchonized with machine clock

#79

· lerwys opened

on Jun 26, 2020

Allow simulataneous range selection on XBPM gateware

#78

· danielot opened

on Jun 10, 2020

[wb_trigger] Add enable input in each logical trigger

#74

· danielot opened

on Aug 18, 2018

[acq_core] More options for data-driven trigger

#71

· danielot opened

on Jul 13, 2017

[wb_trigger_iface] Missing pulse extender check if length = 0

#69

· lerwys opened

on Jun 23, 2017

[flash_loader] Implement Flash Loader via PCIe/Wishbone

#55

· lerwys opened

on Apr 27, 2016

[fmc130m] Top .ucf .xdc files for FMC130M are misleading

#53

· lerwys opened

on Feb 19, 2016

[vivado_project] AXI Interconnect BPM is not generated as VHDL and simulation fails

#51

· lerwys opened

on Dec 18, 2015

[pcie_core] Cannot access DDR data from high address

#45

· lerwys opened

on Jun 12, 2015