CMOS XOR Gate design using Cadence Virtuoso including schematic design, simulation and layout verification (DRC, LVS REX).
This repository presents the complete design and verification flow of a CMOS XOR gate implemented using Cadence Virtuoso. The project demonstrates a full custom VLSI design methodology including schematic design, symbol generation, functional simulation, layout implementation, physical verification, and parasitic extraction.
The XOR gate is an important combinational logic element widely used in arithmetic circuits such as adders, parity generators, comparators, and error detection systems.
Technology : CMOS Design Tool : Cadence Virtuoso Simulation Tool : Spectre Simulator Verification : DRC, LVS Extraction : RC Parasitic Extraction Design Style : Full Custom VLSI
The Exclusive OR (XOR) gate produces a HIGH output when the two inputs are different and LOW when both inputs are the same.
Boolean Expression
Y = A ⊕ B
Expanded Expression
Y = A'B + AB'
Truth Table
| A | B | Y |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
The XOR gate therefore acts as a difference detector between two digital signals.
The XOR gate is implemented using complementary PMOS and NMOS transistor networks forming pull-up and pull-down paths.
Pull-Up Network (PMOS) Connects the output to VDD when the XOR logic condition is satisfied.
Pull-Down Network (NMOS) Connects the output to GND when the XOR condition is not satisfied.
This complementary configuration ensures:
• Low static power consumption • High noise margin • Reliable switching characteristics
The design follows the standard full-custom IC design flow used in semiconductor industry.
- Logic design and Boolean verification
- Transistor level schematic implementation
- Symbol creation for hierarchical usage
- Testbench design and functional simulation
- Layout implementation following design rules
- Design Rule Check (DRC) verification
- Layout Versus Schematic (LVS) verification
- RC parasitic extraction for post-layout analysis
The transistor-level schematic of the XOR gate was implemented in Cadence Virtuoso using CMOS transistors to realize the XOR Boolean function.
A symbol view of the XOR gate was generated to enable hierarchical design and reuse in larger digital circuits.
A testbench circuit was created to apply input stimulus signals and verify the functionality of the XOR gate.
Transient simulation confirms correct XOR functionality where the output becomes HIGH only when the two input signals differ.
The layout was implemented following standard CMOS layout practices including proper placement of NMOS and PMOS devices, routing using metal layers, and well contacts.
DRC verification ensures that the layout satisfies all fabrication design rules defined by the technology file.
LVS verification confirms that the layout connectivity matches the schematic netlist.
The LVS result confirms that the schematic and layout are electrically identical.
Parasitic extraction identifies resistance and capacitance introduced by interconnects in the physical layout.
The RC network represents extracted parasitic components used for accurate post-layout simulation.
Correct XOR logic functionality verified DRC passed successfully LVS matched successfully Parasitic RC extraction completed
Cadence Virtuoso