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1. VGA-interface-using-Verilog VGA-interface-using-Verilog Public

   This repository contains the work done for displaying an image using Basys3 board and VGA interface.

   Verilog 2

2. FullAdder_1bit FullAdder_1bit Public

   Full Adder Module using Half Adder as sub modules

   Verilog

3. Ripple-Carry-Adder Ripple-Carry-Adder Public

   A verilog implementation of a Ripple Carry Adder

   Verilog

4. FullSubtractor_1bit FullSubtractor_1bit Public

   Full Subtractor using Half Subtractor

   Verilog

5. Multiplexer Multiplexer Public

   This repository contains the source file and the test benches for an 8 to 1 Line Mux, using 2 to 1 Line Mux,. The files for both the 2to1 Line Mux and 8to1 Line Mux can be found here.

   Verilog

6. Demultiplexer Demultiplexer Public

   Verilog Design files for Demultiplexer

   Verilog