APB4 Master / Slave UVM Lab

Public APB4 verification lab with original RTL examples and two regressions:

Regression	DUT	UVM role	Result
run_slave_dut.do	APB4 register-bank slave	Active master agent, monitor, scoreboard, coverage	APB4_UVM_LAB_PASS
run_master_dut.do	APB4 request-to-bus master	Reactive slave driver with randomized wait states	APB4_MASTER_DUT_PASS

Architecture

Slave DUT regression:
  random sequence -> APB master driver -> slave DUT -> monitor -> scoreboard + coverage

Master DUT regression:
  random sequence -> local request -> master DUT -> reactive APB slave driver -> checker

The slave supports aligned 32-bit register access and byte strobes. The master converts local requests into APB setup/access phases and captures read/error responses. apb4_checker.sv checks setup/access progression, PSEL / PENABLE relationship and control stability during wait states.

Run

PowerShell:

cd sim
powershell -ExecutionPolicy Bypass -File .\run_all.ps1

QuestaSim GUI:

cd sim
do run_slave_dut.do
do run_master_dut.do

The scripts default to C:/questasim64_10.2c.