😄
Open to Work
RTL Design and Verification Engineer with skill in UVM, SytemVerilog, Verilog, C/C++, Linux, SoC, CPU Design
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3ST Technologies
- New Delhi
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19:41
(UTC +05:30) - in/kashaan-ahmad
- https://leetcode.com/u/MohdKashaan/
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FPGA-Digital-Clock
FPGA-Digital-Clock PublicThis Repository contains about the Design and Implementation of an Digital Clock with Alarm Functionality and Implemented on the Artix 7 Basys 3 FPGA Board.
Verilog 2
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