RISC-V-Microprocessor

Tools Used

Gowin IDE: While there are many great IDE's out there such as Vivado and Quartus, I choose to use Gowin's IDE as I wish to eventually implement the RISC-V microprocessor onto a Tang Nano 9K and it's an easily setup making it very beginner friendly. If you wish to install or buy a Tang Nano 9K FPGA, I've attached links that you'd find helpful.

Phase 1: RTL Design (Current Phase)

Write a fully functional RTL Design of a 5 Cycle Pipelined RV32I CPU in Verilog.

Component TODO List

• Program Counter
• Instruction Memory
• Register File
• Extend Unit
• Data Memory
• Control Unit
• IF/ID Register
• ID/EX Register
• EX/MEM Register
• MEM/WB Register
• Datapath
• Hazard Detection
• Flush Logic
• Full RV32I Implementation

Phase 2: Digital Verification

Verify the functionality of the RTL Design (Phase 1) via SystemVerilog Testbenches

Component TODO List

• Program Counter
• Instruction Memory
• Register File
• Extend Unit
• Data Memory
• Control Unit
• IF/ID Register
• ID/EX Register
• EX/MEM Register
• MEM/WB Register
• Datapath
• Hazard Detection
• Flush Logic
• Full RV32I Implementation

Phase 3: Formal Verification

Write mathematical rules (assertions) in SVA using the open-source tool SymbiYosys (SBY)