A Verilog HDL implementation of an AMBA AHB-inspired interconnect system featuring a Single Master, Four Memory-Mapped Slaves, Address Decoder, Response Multiplexer, and FSM-Based Read/Write Transactions.
The Advanced Microcontroller Bus Architecture (AMBA) is an industry-standard on-chip communication protocol developed by ARM. The Advanced High-performance Bus (AHB) is designed to provide high-speed communication between processors, memories, and peripherals within a System-on-Chip (SoC).
This project implements a simplified AHB-inspired interconnect consisting of a single master and four memory-mapped slaves. The design demonstrates address decoding, slave selection, read/write transactions, and response multiplexing using Verilog HDL.
User Inputs
↓
AHB Master
↓
Decoder
↓
Selected Slave
↓
Memory Read / Write
↓
Multiplexer
↓
Master Response
The objective of this project is to design and verify a bus architecture capable of:
- Selecting one of four slaves
- Performing read transactions
- Performing write transactions
- Routing responses back to the master
- Demonstrating hierarchical RTL design
- Verifying functionality through simulation
The AMBA AHB interconnect consists of a Single Master, Decoder, Four Memory-Mapped Slaves, and a Response Multiplexer. The master initiates all bus transactions while the decoder selects the target slave based on the selection input.
| Block | Function | Inputs | Outputs |
|---|---|---|---|
| AHB Master | Generates read/write transactions and controls bus operation through FSM states. | enable, data_in_a, data_in_b, addr, wr, slave_sel, hreadyout, hrdata | haddr, hwdata, hwrite, htrans, hsize, hburst, hprot, sel, sel_valid |
| Decoder | Converts slave selection into one-hot slave enable signals. | sel, sel_valid | hsel_1, hsel_2, hsel_3, hsel_4 |
| AHB Slave 1 | 32-word memory used for read/write transactions. | hsel_1 and bus signals | hrdata_1, hreadyout_1, hresp_1 |
| AHB Slave 2 | 32-word memory used for read/write transactions. | hsel_2 and bus signals | hrdata_2, hreadyout_2, hresp_2 |
| AHB Slave 3 | 32-word memory used for read/write transactions. | hsel_3 and bus signals | hrdata_3, hreadyout_3, hresp_3 |
| AHB Slave 4 | 32-word memory used for read/write transactions. | hsel_4 and bus signals | hrdata_4, hreadyout_4, hresp_4 |
| Multiplexer | Selects response from active slave and routes it back to the master. | hrdata_x, hreadyout_x, hresp_x | hrdata, hreadyout, hresp |
The master computes:
HWDATA = DATA_IN_A + DATA_IN_B
The generated data is written into the selected slave memory. During a read operation, the selected slave returns data through the multiplexer and the master asserts read_complete.
The system consists of an AHB Master, Decoder, Four Memory-Mapped Slaves, and a Multiplexer that returns the selected slave response to the master.
The RTL schematic generated using Vivado verifies the complete connectivity between all modules and demonstrates the hierarchical hardware implementation of the design.
- Master-to-Slave Communication
- Decoder-Based Slave Selection
- Shared Bus Architecture
- Four Independent Slave Memories
- Multiplexed Response Routing
The design was verified using a dedicated testbench. Four independent transactions were performed to validate correct operation of all four memory-mapped slaves.
- hclk
- enable
- slave_sel
- haddr
- hwdata
- hrdata
- hsel_1
- hsel_2
- hsel_3
- hsel_4
- read_complete
- FSM state transitions
- htrans
- Slave Selected = 00 (Slave 1)
- Address = 1
- DATA_IN_A = 0x55555555
- DATA_IN_B = 0xAAAAAAAA
- Master computes HWDATA = 0xFFFFFFFF
- Decoder activates hsel_1
- Data is written into Slave 1 memory
- Read transaction returns 0xFFFFFFFF
- read_complete asserted successfully
- FSM transitions IDLE → ADDR → DATA → IDLE
- Slave Selected = 01 (Slave 2)
- Address = 2
- DATA_IN_A = 0xCAFE0000
- DATA_IN_B = 0x0000BABE
- Master computes HWDATA = 0xCAFEBABE
- Decoder activates hsel_2
- Data is stored inside Slave 2 memory
- Read operation retrieves 0xCAFEBABE
- Multiplexer forwards Slave 2 response
- read_complete asserted successfully
- Slave Selected = 10 (Slave 3)
- Address = 3
- DATA_IN_A = 0x12345678
- DATA_IN_B = 0x87654321
- Master computes HWDATA = 0x99999999
- Decoder activates hsel_3
- Data written into Slave 3 memory
- Read operation returns 0x99999999
- Correct slave response selected by multiplexer
- Transaction completed successfully
- Slave Selected = 11 (Slave 4)
- Address = 4
- DATA_IN_A = 0xDEAD0000
- DATA_IN_B = 0x0000BEEF
- Master computes HWDATA = 0xDEADBEEF
- Decoder activates hsel_4
- Data written into Slave 4 memory
- Read operation returns 0xDEADBEEF
- Response routed through multiplexer
- read_complete asserted successfully
- Address Generation
- Slave Selection
- Write Transactions
- Read Transactions
- Read Completion Signaling
- FSM State Transitions
- Reset Verification
- Slave 1 Write and Read Transaction
- Slave 2 Write and Read Transaction
- Slave 3 Write and Read Transaction
- Slave 4 Write and Read Transaction
- Read Completion Verification
- FSM State Verification
- Decoder Verification
- Multiplexer Verification
+----------------+
| AHB MASTER |
+--------+-------+
|
v
+----------------+
| DECODER |
+--------+-------+
|
+------------+------+------+------------+
| | | |
v v v v
+------+ +------+ +------+ +------+
|SLV 1 | |SLV 2 | |SLV 3 | |SLV 4 |
+------+ +------+ +------+ +------+
| | | |
+------------+------+------+------------+
|
v
+----------------+
| MULTIPLEXER |
+--------+-------+
|
v
Master Response
| Module | Function |
|---|---|
| ahb_master | Generates AHB transactions and controls bus operation |
| decoder | Selects one of four slaves |
| ahb_slave | Stores and retrieves data from memory |
| multiplexer | Routes selected slave response back to master |
| ahb_top | Integrates all modules into a complete system |
| ahb_top_tb | Verifies design functionality through simulation |
The repository is organized into separate directories for RTL source files, testbench verification files, and project documentation resources.
AMBA-AHB-Single-Master-4-Slave
│
├── README.md
│
├── images
├── intro_ahb.png
├── func_block_diagram.png
├── rtl_structure.png
├── sim_waveform_1.png
├── sim_waveform_2.png
├── sim_waveform_3.png
└── sim_waveform_4.png
│
├── rtl
│ ├── ahb_master.v
│ ├── ahb_slave.v
│ ├── decoder.v
│ ├── multiplexer.v
│ └── ahb_top.v
│
└── tb
└── ahb_top_tb.v
images/ contains architectural diagrams, RTL schematics, and simulation waveforms used throughout the documentation.
rtl/ contains synthesizable Verilog source files implementing the AMBA AHB Single Master 4-Slave architecture.
tb/ contains the verification environment used to validate read and write transactions through simulation.
The master receives user inputs and initiates transactions through a finite state machine.
- IDLE : Waits for a transaction request.
- ADDR : Captures address and control information.
- DATA : Performs read/write operation and completes the transfer.
For write operations:
HWDATA = DATA_IN_A + DATA_IN_B
The computed value is stored in the selected slave memory.
For read operations, data is fetched from the selected slave and returned through the multiplexer. A read_complete signal indicates successful completion of the read transaction.
Slave Memory
↓
Multiplexer
↓
HRDATA
↓
AHB Master
↓
read_complete
- FSM-Based Controller
- Address Generation
- Slave Selection
- Arithmetic Operation (A + B)
- Read/Write Transaction Control
- Read Completion Generation
sel = 00 → hsel_1 sel = 01 → hsel_2 sel = 10 → hsel_3 sel = 11 → hsel_4
- Converts slave selection into one-hot slave enable signals
- Activates only one slave at a time
- Each slave contains a 32 × 32-bit memory array.
- Total memory per slave = 1024 bits.
- Total memory across four slaves = 4096 bits.
- 32 × 32 Memory Array
- Read Support
- Write Support
- Response Generation
- Selects active slave response
- Routes data back to master
- Selects hrdata, hreadyout, and hresp signals
- Single Master Architecture
- Four Memory-Mapped Slaves
- Decoder-Based Slave Selection
- Response Multiplexer
- FSM-Based Transaction Controller
- Read Transactions
- Write Transactions
- Arithmetic Data Generation (A + B)
- Read Completion Signaling
- RTL Verification
- Simulation Verification
- Verilog HDL
- Xilinx Vivado
- Vivado Simulator
- RTL Schematic Viewer
- GitHub
Ashish Kumar Kashyap
B.Tech Electronics and Communication Engineering
Motilal Nehru National Institute of Technology Allahabad