feature: check resetstatus prior to writing to bus

Author: w531t4

src/matrix_panel_fpga.cpp

@@ -38,6 +38,7 @@ void MatrixPanel_FPGA_SPI::do_swapFrame_() {
     }
     SpiLockGuard spi_lock(this);
     if (!spi_lock.locked())
+    if (!wait_for_fpga_resetstatus_())
         return;
     uint8_t buf[1];
     uint16_t buf_len = 0;
@@ -78,6 +79,7 @@ void MatrixPanel_FPGA_SPI::do_fulfillWatchdog_() {
     }
     SpiLockGuard spi_lock(this);
     if (!spi_lock.locked())
+    if (!wait_for_fpga_resetstatus_())
         return;
     uint8_t buf[9] = {'W',  0xDE, 0xAD, 0xBE, 0xEF,
                       0xFE, 0xEB, 0xDA, 0xED}; // 'W' is
@@ -143,6 +145,22 @@ void MatrixPanel_FPGA_SPI::init_fpga_resetstatus_gpio_() {
     }
 }
 
+bool MatrixPanel_FPGA_SPI::wait_for_fpga_resetstatus_() {
+    if (!fpga_resetstatus_configured_)
+        return true;
+    const TickType_t start = xTaskGetTickCount();
+    const TickType_t timeout =
+        pdMS_TO_TICKS(m_cfg.fpga_resetstatus_timeout_ms);
+    while (gpio_get_level((gpio_num_t)m_cfg.gpio.fpga_resetstatus) == 0) {
+        if ((xTaskGetTickCount() - start) > timeout) {
+            ESP_LOGW("fpga_resetstatus", "Timeout waiting for FPGA resetstatus");
+            return false;
+        }
+        vTaskDelay(1);
+    }
+    return true;
+}
+
 bool MatrixPanel_FPGA_SPI::consume_fpga_reset() {
     if (!fpga_resetstatus_configured_)
         return false;
@@ -203,6 +221,7 @@ void MatrixPanel_FPGA_SPI::do_drawFrameRGB888_(const uint8_t *data,
     }
     SpiLockGuard spi_lock(this);
     if (!spi_lock.locked())
+    if (!wait_for_fpga_resetstatus_())
         return;
 
     const size_t chunk_bytes =
@@ -283,6 +302,7 @@ void MatrixPanel_FPGA_SPI::do_drawRowRGB888_(const uint8_t y,
     }
     SpiLockGuard spi_lock(this);
     if (!spi_lock.locked())
+    if (!wait_for_fpga_resetstatus_())
         return;
 
     uint8_t buf[expected_row_bytes];
@@ -333,6 +353,7 @@ void MatrixPanel_FPGA_SPI::do_drawPixelRGB888_(int16_t x, int16_t y, uint8_t r,
     }
     SpiLockGuard spi_lock(this);
     if (!spi_lock.locked())
+    if (!wait_for_fpga_resetstatus_())
         return;
     uint8_t buf[7];
     uint8_t buf_len = 0;
@@ -393,6 +414,7 @@ void MatrixPanel_FPGA_SPI::do_fillScreenRGB888_(uint8_t r, uint8_t g,
     }
     SpiLockGuard spi_lock(this);
     if (!spi_lock.locked())
+    if (!wait_for_fpga_resetstatus_())
         return;
     uint8_t buf[4];
     uint8_t buf_len = 0;
@@ -438,6 +460,7 @@ void MatrixPanel_FPGA_SPI::do_clearScreen_() {
     }
     SpiLockGuard spi_lock(this);
     if (!spi_lock.locked())
+    if (!wait_for_fpga_resetstatus_())
         return;
     uint8_t buf[1];
     uint8_t buf_len = 0;
@@ -478,6 +501,7 @@ void MatrixPanel_FPGA_SPI::do_setBrightness8_(const uint8_t b) {
     }
     SpiLockGuard spi_lock(this);
     if (!spi_lock.locked())
+    if (!wait_for_fpga_resetstatus_())
         return;
     uint8_t buf[2];
     uint8_t buf_len = 0;
@@ -523,6 +547,7 @@ void MatrixPanel_FPGA_SPI::do_fillRect_(int16_t x, int16_t y, int16_t w,
     }
     SpiLockGuard spi_lock(this);
     if (!spi_lock.locked())
+    if (!wait_for_fpga_resetstatus_())
         return;
     uint8_t buf[10];
     uint8_t buf_len = 0;

src/matrix_panel_fpga.hpp

@@ -136,6 +136,7 @@ class MatrixPanel_FPGA_SPI {
     void do_fulfillWatchdog_();
     void do_setBrightness8_(const uint8_t b);
     void init_fpga_resetstatus_gpio_();
+    bool wait_for_fpga_resetstatus_();
     static void fpga_resetstatus_isr_(void *arg);
     // Matrix i2s settings
     FPGA_SPI_CFG m_cfg;

src/matrix_panel_fpga_config.hpp

@@ -96,16 +96,21 @@ struct FPGA_SPI_CFG {
     // to get all colour depths displayed with correct BCM time weighting.
     uint8_t min_refresh_rate;
 
+    // FPGA status timeouts (milliseconds)
+    uint16_t fpga_resetstatus_timeout_ms;
+
     // struct constructor
     FPGA_SPI_CFG(
         uint16_t _w = MATRIX_WIDTH, uint16_t _h = MATRIX_HEIGHT,
         uint16_t _chain = CHAIN_LENGTH,
         spi_pins _pinmap = {SPI_CE_PIN_DEFAULT, SPI_CLK_PIN_DEFAULT,
                             SPI_MOSI_PIN_DEFAULT, FPGA_RESETSTATUS_PIN_DEFAULT},
         clk_speed _spispeed = HZ_8M, uint16_t _min_refresh_rate = 60,
-        uint8_t _pixel_color_depth_bits = PIXEL_COLOR_DEPTH_BITS_DEFAULT)
+        uint8_t _pixel_color_depth_bits = PIXEL_COLOR_DEPTH_BITS_DEFAULT,
+        uint16_t _fpga_resetstatus_timeout_ms = 1000)
         : mx_width(_w), mx_height(_h), chain_length(_chain), gpio(_pinmap),
-          spispeed(_spispeed), min_refresh_rate(_min_refresh_rate) {
+          spispeed(_spispeed), min_refresh_rate(_min_refresh_rate),
+          fpga_resetstatus_timeout_ms(_fpga_resetstatus_timeout_ms) {
         setPixelColorDepthBits(_pixel_color_depth_bits);
     }