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Commit 17e9714

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feature: remove RESET pin
1 parent 6e2dd7d commit 17e9714

2 files changed

Lines changed: 2 additions & 10 deletions

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src/matrix_panel_fpga.hpp

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -44,12 +44,6 @@ class MatrixPanel_FPGA_SPI {
4444
init_fpga_ready_gpio_();
4545

4646
start_worker();
47-
// Reset the fpga state
48-
gpio_set_direction((gpio_num_t)m_cfg.gpio.fpga_reset, GPIO_MODE_OUTPUT);
49-
gpio_set_level((gpio_num_t)m_cfg.gpio.fpga_reset, 0); // LOW
50-
gpio_set_level((gpio_num_t)m_cfg.gpio.fpga_reset, 1); // HIGH
51-
gpio_set_level((gpio_num_t)m_cfg.gpio.fpga_reset, 0); // LOW
52-
5347
while (!initialized)
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;
5549
if (!initialized) {

src/matrix_panel_fpga_config.hpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,6 @@
1717
#define SPI_MOSI_PIN_DEFAULT 2
1818
#define SPI_CE_PIN_DEFAULT 15
1919

20-
#define FPGA_RESET_PIN_DEFAULT 4
2120
#define FPGA_READY_PIN_DEFAULT -1
2221

2322
// Adapted from
@@ -86,7 +85,7 @@ struct FPGA_SPI_CFG {
8685

8786
// GPIO Mapping
8887
struct spi_pins {
89-
int8_t ce, clk, mosi, fpga_reset, fpga_ready;
88+
int8_t ce, clk, mosi, fpga_ready;
9089
} gpio;
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9291
// SPI clock speed
@@ -102,8 +101,7 @@ struct FPGA_SPI_CFG {
102101
uint16_t _w = MATRIX_WIDTH, uint16_t _h = MATRIX_HEIGHT,
103102
uint16_t _chain = CHAIN_LENGTH,
104103
spi_pins _pinmap = {SPI_CE_PIN_DEFAULT, SPI_CLK_PIN_DEFAULT,
105-
SPI_MOSI_PIN_DEFAULT, FPGA_RESET_PIN_DEFAULT,
106-
FPGA_READY_PIN_DEFAULT},
104+
SPI_MOSI_PIN_DEFAULT, FPGA_READY_PIN_DEFAULT},
107105
clk_speed _spispeed = HZ_8M, uint16_t _min_refresh_rate = 60,
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uint8_t _pixel_color_depth_bits = PIXEL_COLOR_DEPTH_BITS_DEFAULT)
109107
: mx_width(_w), mx_height(_h), chain_length(_chain), gpio(_pinmap),

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