'clock_period' for synthesize

1. Configs in /WORK_REPO/CGRA-Flow/tools/mflowgen/designs/cgra/construct-open.py, clock_period is in ns here (i.e., 2.0ns -> 500 MHz). https://github.com/tancheng/mflowgen/blob/2b047fc96cf3c44799eaf20fbb68eefe0b48a593/designs/cgra/construct-open.py#L28

  parameters = {
    'construct_path' : __file__,
    'design_name'    : 'CgraTemplateRTL',
    'clock_period'   : 2000.0,
    'adk'            : adk_name,
    'adk_view'       : adk_view,
  }

2. Clicks synthesize in UI, it runs: mflowgen run --design ../designs/cgra

3. Generates configure.yml in path: /WORK_REPO/CGRA-Flow/tools/mflowgen/build/3-open-yosys-synthesis

...
name: open-yosys-synthesis
outputs:
- design.v
- synth.stats.txt
parameters:
  clock_period: 2000.0
  design_name: CgraTemplateRTL
source: /WORK_REPO/CGRA-Flow/tools/mflowgen/steps/open-yosys-synthesis

4. Generates synth.ys based on synth.ys.template to replace variables (clock_period_ps is in ps):

synth.ys.template:

...
# opt

# Technology mapping for combinational cells

#abc -exe yosys-abc -liberty inputs/adk/stdcells.lib \
#    -script +strash;scorr;ifraig;retime,{{D}};strash;dch,-f;map,-M,1,{{D}}

abc -liberty inputs/adk/stdcells.lib \
    -D {clock_period_ps} -constr {constraints_tcl}
...

synth.ys:

...
# opt

# Technology mapping for combinational cells

#abc -exe yosys-abc -liberty inputs/adk/stdcells.lib \
#    -script +strash;scorr;ifraig;retime,{D};strash;dch,-f;map,-M,1,{D}

abc -liberty inputs/adk/stdcells.lib \
    -D 2000000.0 -constr constraints.tcl
...

5. Yosys to run synthesize