clean code and add openroad install steps in Dockerfile

Author: yuqisun

docker/Dockerfile

@@ -3,10 +3,13 @@ FROM ubuntu:22.04
 SHELL ["/bin/bash", "-c"]
 
 ENV DEBIAN_FRONTEND=noninteractive
-ENV PATH="/WORK_REPO/verilator/bin:$PATH"
 ENV VERILATOR_ROOT=/WORK_REPO/verilator
 ENV PYMTL_VERILATOR_INCLUDE_DIR=/WORK_REPO/verilator/share/verilator/include
 ENV PATH="/WORK_REPO/CGRA-Flow/tools/sv2v/bin:$PATH"
+ENV PATH="/WORK_REPO/CGRA-Flow/tools/oss-cad-suite/bin:$PATH"
+ENV YOSYS_EXE="/WORK_REPO/CGRA-Flow/tools/oss-cad-suite/bin/yosys"
+ENV OPENROAD_EXE="/usr/bin/openroad"
+ENV PATH="/WORK_REPO/verilator/bin:$PATH"
 
 RUN mkdir /WORK_REPO \
     && cd /WORK_REPO \
@@ -77,7 +80,20 @@ RUN mkdir /WORK_REPO \
     && cd /WORK_REPO/CGRA-Flow \
     && mkdir build && cd build \
     && cp ../docker/config.mk ./ \
-    && cp ../docker/constraint.sdc ./
+    && cp ../docker/constraint.sdc ./ \
+    # Install OpenROAD
+    && cd /WORK_REPO/CGRA-Flow/tools \
+    && wget https://github.com/Precision-Innovations/OpenROAD/releases/download/2024-08-05/openroad_2.0_amd64-ubuntu22.04-2024-08-05.deb \
+    && wget https://www.klayout.org/downloads/Ubuntu-22/klayout_0.29.6-1_amd64.deb \
+    && wget https://github.com/YosysHQ/oss-cad-suite-build/releases/download/2024-09-20/oss-cad-suite-linux-x64-20240920.tgz \
+    && apt-get update \
+    && apt-get install -y --fix-broken \
+    && dpkg -i klayout_0.29.6-1_amd64.deb || true \
+    && apt-get install -y --fix-broken \
+    && tar zxvf oss-cad-suite-linux-x64-20240920.tgz -C ./ \
+    && apt-get install -y ./openroad_2.0_amd64-ubuntu22.04-2024-08-05.deb \
+    && apt-get install -y time \
+    && rm -f *.deb *.tgz
 
 WORKDIR "/WORK_REPO/CGRA-Flow/build"
 #CMD ["/WORK_REPO/venv/bin/python", "../mode_dark_light.py"]

docker/config.mk

@@ -0,0 +1,35 @@
+export PLATFORM     	= asap7
+export DESIGN_NAME  	= CgraTemplateRTL
+export VERILOG_FILES	= $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
+export SDC_FILE     	= ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
+#export ABC_AREA             	= 1
+export SYNTH_HIERARCHICAL = 1
+export RTLMP_FLOW = True
+export ENABLE_DPO = True
+export CORE_UTILIZATION     	= 15
+export CORE_ASPECT_RATIO    	= 1
+export GPL_ROUTABILITY_DRIVEN  = 1
+export CORE_MARGIN          	= 5
+export PLACE_DENSITY        	= 0.3
+export TNS_END_PERCENT      	= 100
+export CTS_BUF_CELL  = BUFx8_ASAP7_75t_R
+#export CTS_BUF_DISTANCE = 10000
+# If this design isn't quickly done in detailed routing, something is wrong.
+# At time of adding this option, only 12 iterations were needed for 0
+# violations.
+export DETAILED_ROUTE_ARGS   = -bottom_routing_layer M2 -top_routing_layer M9 -save_guide_updates -verbose 1 -droute_end_iter 45
+export RECOVER_POWER = 50
+# since we are specifying DETAILED_ROUTE_ARGS, we need to communicate the
+# same information to other stages in the flow.
+export MIN_ROUTING_LAYER = M2
+export MAX_ROUTING_LAYER = M9
+
+# works with 28 or more iterations as of writing, so give it a few more.
+export GLOBAL_ROUTE_ARGS=-congestion_iterations 40 -verbose
+#export FASTROUTE_TCL = ./designs/$(PLATFORM)/TileRTL__286c363070523335/fastroute.tcl
+
+export configure_cts_characterization  [-max_slew max_slew][-max_cap max_cap][-slew_steps slew_steps] [-cap_steps cap_steps]
+	 
+export global_placement  [-routability_driven] [-routability_check_overflow routability_check_overflow] [-routability_max_density routability_max_density]
+#export detailed_route_debug -dr
+export REMOVE_CELLS_FOR_EQY 	= TAPCELL*

docker/constraint.sdc

@@ -0,0 +1,16 @@
+current_design CgraTemplateRTL
+
+set clk_name  core_clock
+set clk_port_name clk
+set clk_period 1000000
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_port_name]
+
+create_clock -name $clk_name -period $clk_period  $clk_port
+
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+
+set_input_delay  [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
+

docker/openroad_urls.txt

@@ -793,12 +793,6 @@ def clickShowDFG():
         "enablePowerGating"     : False
     }
 
-    # json_object = json.dumps(genDFGJson, indent=4)
-
-    # with open("param.json", "w") as outfile:
-    #     outfile.write(json_object)
-
-    # dumpCgraParam2JSON("paramCGRA.json")
     dumpCgraParam2JSON("param.json", genDFGJson)
 
     genDFGCommand = "opt-12 -load ../../CGRA-Mapper/build/src/libmapperPass.so -mapperPass ./kernel.bc"
@@ -1053,12 +1047,6 @@ def clickMapDFG():
         "enablePowerGating"     : False,
     }
 
-    # mappingJsonObject = json.dumps(mappingJson, indent=4)
-
-    # with open("param.json", "w") as outfile:
-        # outfile.write(mappingJsonObject)?
-
-    # dumpCgraParam2JSON("paramCGRA.json")
     dumpCgraParam2JSON("param.json", mappingJson)
 
     mappingCommand = "opt-12 -load ../../CGRA-Mapper/build/src/libmapperPass.so -mapperPass ./kernel.bc"