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Commit 029b257

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Merge pull request #3 from makslevental/max_op
Max op
2 parents bdc0231 + 46aba48 commit 029b257

142 files changed

Lines changed: 76572 additions & 55746 deletions

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bragghls/compiler/compile.py

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -203,7 +203,7 @@ def compile(
203203
vals,
204204
csts,
205205
pe_idxs,
206-
for_testbench=do_testbench
206+
for_testbench=do_testbench,
207207
)
208208
verilog_file = verilog_file.replace("%", "p_")
209209
with open(f"{artifacts_dir}/{name}.sv", "w") as f:
@@ -224,9 +224,12 @@ def compile(
224224
logger.info(f"RTL top-level {name}")
225225

226226
for ip_core_sv in [
227-
f"flopoco_fadd_{width_exponent}_{width_fraction}.sv",
228-
f"flopoco_fmul_{width_exponent}_{width_fraction}.sv",
229-
f"flopoco_fdiv_{width_exponent}_{width_fraction}.sv",
227+
f"fadd/flopoco_fadd_{width_exponent}_{width_fraction}.sv",
228+
f"fsub/flopoco_fsub_{width_exponent}_{width_fraction}.sv",
229+
f"fmul/flopoco_fmul_{width_exponent}_{width_fraction}.sv",
230+
f"fdiv/flopoco_fdiv_{width_exponent}_{width_fraction}.sv",
231+
f"fcmplt/flopoco_fcmplt_{width_exponent}_{width_fraction}.sv",
232+
f"flopoco_max.sv",
230233
f"flopoco_neg.sv",
231234
f"flopoco_relu.sv",
232235
f"alveo-u280-xdc.xdc",
@@ -251,7 +254,6 @@ def compile(
251254
},
252255
width_exponent=width_exponent,
253256
width_fraction=width_fraction,
254-
ip_cores_path=os.path.dirname(ip_cores.__file__),
255257
n_test_vectors=n_test_vectors,
256258
threshold=threshold,
257259
)

bragghls/compiler/state.py

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
import networkx as nx
44

55
from bragghls.config import VAL_PREFIX, DTYPE, DEBUG, INCLUDE_AUX_DEPS
6+
from bragghls.util import extend_idx
67

78
logging.basicConfig(encoding="utf-8", level=logging.INFO)
89
logger = logging.getLogger(__name__)
@@ -98,7 +99,8 @@ def update_current_pe_idx(self, *, pe_idx=None, val=None):
9899
src = self.get_arg_src(val)
99100
if isinstance(src, str):
100101
assert src in {INPUT_ARG, MEMREF_ARG, GLOBAL_MEMREF_ARG, CONSTANT}
101-
return
102+
if src in {MEMREF_ARG, GLOBAL_MEMREF_ARG}:
103+
self.pe_idx = extend_idx(tuple(map(int, val.id.split("_"))))
102104
else:
103105
self.pe_idx = src.pe_idx
104106
else:

bragghls/config.py

Lines changed: 16 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -33,38 +33,43 @@
3333
pipeline_depth_re = re.compile(r"Pipeline depth: (\d+) cycles")
3434
with open(
3535
Path(ip_cores.__file__).parent
36+
/ "fmul"
3637
/ f"flopoco_fmul_{WIDTH_EXPONENT}_{WIDTH_FRACTION}.vhdl"
3738
) as f:
3839
depths = pipeline_depth_re.findall(f.read())
3940
MUL_PIPELINE_DEPTH = int(depths[-1])
4041
with open(
4142
Path(ip_cores.__file__).parent
43+
/ "fadd"
4244
/ f"flopoco_fadd_{WIDTH_EXPONENT}_{WIDTH_FRACTION}.vhdl"
4345
) as f:
4446
depths = pipeline_depth_re.findall(f.read())
4547
ADD_PIPELINE_DEPTH = int(depths[-1])
4648
with open(
4749
Path(ip_cores.__file__).parent
50+
/ "fsub"
51+
/ f"flopoco_fsub_{WIDTH_EXPONENT}_{WIDTH_FRACTION}.vhdl"
52+
) as f:
53+
depths = pipeline_depth_re.findall(f.read())
54+
SUB_PIPELINE_DEPTH = int(depths[-1])
55+
with open(
56+
Path(ip_cores.__file__).parent
57+
/ "fdiv"
4858
/ f"flopoco_fdiv_{WIDTH_EXPONENT}_{WIDTH_FRACTION}.vhdl"
4959
) as f:
5060
depths = pipeline_depth_re.findall(f.read())
5161
DIV_PIPELINE_DEPTH = int(depths[-1])
52-
else:
53-
MUL_PIPELINE_DEPTH = int(
54-
os.getenv("MUL_PIPELINE_DEPTH") or config["ip"].get("MulPipelineDepth")
55-
)
56-
DIV_PIPELINE_DEPTH = int(
57-
os.getenv("DIV_PIPELINE_DEPTH") or config["ip"].get("DivPipelineDepth")
58-
)
59-
# DIV_RADIX = int(os.getenv("DIV_RADIX") or config["ip"].get("DivRadix"))
60-
ADD_PIPELINE_DEPTH = int(
61-
os.getenv("ADD_PIPELINE_DEPTH") or config["ip"].get("AddPipelineDepth")
62-
)
6362

6463
MUL_LATENCY = MUL_PIPELINE_DEPTH + 1
6564
DIV_LATENCY = DIV_PIPELINE_DEPTH + 1
6665
ADD_LATENCY = ADD_PIPELINE_DEPTH + 1
66+
SUB_LATENCY = SUB_PIPELINE_DEPTH + 1
6767

68+
# comb ops with registered outputs
69+
MAX_LATENCY = 2
70+
GT_LATENCY = 2
71+
NEG_LATENCY = 2
72+
RELU_LATENCY = 2
6873

6974
_nameToLevel = {
7075
"CRITICAL": logging.CRITICAL,

bragghls/flopoco/convert_flopoco.py

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,9 @@
1212

1313
def convert_flopoco_binary_str_to_float(s, width_exp, width_frac):
1414
assert len(s) == width_exp + width_frac + 2 + 1
15-
return float(flopoco_converter.bin2fp(width_exp, width_frac, s))
15+
return float(
16+
flopoco_converter.bin2fp(width_exp, width_frac, s).strip().replace("\x01", "")
17+
)
1618

1719

1820
if __name__ == "__main__":
Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,14 @@
11
#!/usr/bin/env python3
22
import sys
33

4-
from bragghls.flopoco.convert_flopoco import convert_flopoco_binary_str_to_float
4+
from convert_flopoco import convert_flopoco_binary_str_to_float
55

66

77
def main():
88
fh_in = sys.stdin
99
fh_out = sys.stdout
1010

11-
width_exponent = width_fraction = 8
11+
width_exponent = width_fraction = 4
1212
while True:
1313
# incoming values have newline
1414
l = fh_in.readline()
@@ -27,8 +27,8 @@ def main():
2727
)
2828
fh_out.write("%s\n" % s)
2929
except Exception as e:
30-
print(e, file=sys.stderr)
31-
fh_out.write("%s" % l)
30+
# print(e, file=sys.stderr)
31+
fh_out.write("%s\n" % l)
3232
fh_out.flush()
3333

3434

bragghls/flopoco/ops.py

Lines changed: 47 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,35 +1,46 @@
1+
import operator
12
from collections import namedtuple
23
from dataclasses import dataclass
34
from functools import reduce
45

56
import numpy as np
67

7-
from bragghls.compiler import state
8-
from bragghls.config import WIDTH_EXPONENT, WIDTH_FRACTION
9-
from bragghls.util import idx_to_str, chunks
10-
118
try:
129
from . import flopoco_converter
1310
except:
1411
import flopoco_converter
1512

13+
from bragghls.compiler import state
14+
from bragghls.config import WIDTH_EXPONENT, WIDTH_FRACTION
15+
from bragghls.util import idx_to_str, chunks
16+
1617
FPNUMBER = namedtuple("FPNUMBER", "pe_idx")(None)
1718

1819

19-
def reducer(accum, val):
20+
def reducer(accum, val, reduce_op):
2021
if len(val) > 1:
21-
return accum + [val[0] + val[1]]
22+
res = reduce_op(val[0], val[1])
23+
return accum + [res]
2224
else:
2325
return accum + val
2426

2527

2628
def ReduceAdd(vals):
2729
pairs = list(chunks(list(vals), 2))
2830
while len(pairs) > 1:
29-
pairs = list(chunks(reduce(reducer, pairs, []), 2))
31+
pairs = list(
32+
chunks(reduce(lambda x, y: reducer(x, y, operator.add), pairs, []), 2)
33+
)
3034
return pairs[0][0] + pairs[0][1]
3135

3236

37+
def ReduceMax(vals):
38+
pairs = list(chunks(list(vals), 2))
39+
while len(pairs) > 1:
40+
pairs = list(chunks(reduce(lambda x, y: reducer(x, y, max), pairs, []), 2))
41+
return max(pairs[0][0], pairs[0][1])
42+
43+
3344
def check_make_val(v, width_exponent, width_fraction):
3445
if not isinstance(v, Val):
3546
assert isinstance(v, (float, int)), v
@@ -70,6 +81,12 @@ def __eq__(self, other):
7081
other = check_make_val(other, self.width_exponent, self.width_fraction)
7182
return self.fp == other.fp
7283

84+
def __lt__(self, other):
85+
other = check_make_val(other, self.width_exponent, self.width_fraction)
86+
# print(self.fp, other.fp, self.fp - other.fp, (self.fp - other.fp).sign())
87+
# print((self.fp - other.fp).sign())
88+
return (self.fp - other.fp).sign() == 1
89+
7390
def __add__(self, other):
7491
other = check_make_val(other, self.width_exponent, self.width_fraction)
7592
v = add(self, other)
@@ -97,6 +114,10 @@ def __repr__(self):
97114
f"<IEEE {self.ieee:.5e}> {self.fp} {self.width_exponent} {self.width_fraction}"
98115
)
99116

117+
@property
118+
def fp_float(self):
119+
return float(f"{str(self.fp).split(':')[0].split(' ')[1]}")
120+
100121

101122
def mul(x: Val, y: Val):
102123
assert x.width_exponent == y.width_exponent
@@ -171,6 +192,9 @@ def numel(self):
171192
def reduce_add(self):
172193
return ReduceAdd(self.registers.flatten())
173194

195+
def reduce_max(self):
196+
return ReduceMax(list(self.registers.flatten()))
197+
174198
@property
175199
def val_names_map(self):
176200
assert self.input or self.output
@@ -250,6 +274,9 @@ def __getitem__(self, index):
250274
def numel(self):
251275
return np.prod(self.shape)
252276

277+
def reduce_max(self):
278+
return ReduceMax(list(self.vals.flatten()))
279+
253280
@staticmethod
254281
def from_global_memref(memref, width_exponent, width_fraction):
255282
return GlobalMemRef(
@@ -302,8 +329,19 @@ def Div(cst, val):
302329

303330

304331
def main():
305-
five = Val(4.0, 4, 4)
306-
print(Div(1.0, five))
332+
a = Val(2, 4, 4)
333+
b = Val(1, 4, 4)
334+
print(a - a)
335+
print(a, b)
336+
print(a - b)
337+
a = flopoco_converter.FPNumber(2, 4, 4)
338+
b = flopoco_converter.FPNumber(1, 4, 4)
339+
print(a + a)
340+
print(a - a)
341+
print(a - b)
342+
print(b - b)
343+
print(a - b)
344+
print(a + b)
307345

308346

309347
if __name__ == "__main__":

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