more vlog

Author: Zaneham

src/emit/tk_vlog.c

@@ -390,6 +390,99 @@ em_vlog(const rt_mod_t *M, const lb_lib_t *lib,
     }
     fprintf(fp, "\n");
 
+    /* ---- Inferred memories ---- */
+    for (i = 0; i < M->n_mem; i++) {
+        const char *mnam = M->strs + M->mems[i].name_off;
+        uint32_t dw = M->mems[i].data_w;
+        uint32_t dp = M->mems[i].depth;
+
+        fprintf(fp, "// Memory: %.*s (%ux%u)\n",
+                (int)M->mems[i].name_len, mnam, dp, dw);
+        fprintf(fp, "reg [%u:0] %.*s [0:%u];\n",
+                dw - 1, (int)M->mems[i].name_len, mnam, dp - 1);
+
+        /* Memory writes are synchronous, so we need a clock.
+         * Borrow it from the first DFF we find — they all
+         * share the same clock in a single-clock design. */
+        {
+            uint32_t clk_net = 0;
+            uint32_t ci;
+            for (ci = 1; ci < M->n_cell; ci++) {
+                if ((M->cells[ci].type == RT_DFF ||
+                     M->cells[ci].type == RT_DFFR) &&
+                    M->cells[ci].n_in >= 2) {
+                    clk_net = M->cells[ci].ins[1];
+                    break;
+                }
+            }
+
+            /* Reconstruct the always block from MEMWR cells.
+             * The third input, if present, is the write-enable. */
+            {
+                uint32_t waddr = 0, wdata = 0, we_net = 0;
+                uint32_t ci2;
+                for (ci2 = 1; ci2 < M->n_cell; ci2++) {
+                    if (M->cells[ci2].type == RT_MEMWR &&
+                        M->cells[ci2].param == (int64_t)i) {
+                        waddr = M->cells[ci2].ins[0];
+                        wdata = M->cells[ci2].ins[1];
+                        if (M->cells[ci2].n_in >= 3)
+                            we_net = M->cells[ci2].ins[2];
+                        break;
+                    }
+                }
+
+                if (waddr > 0 && wdata > 0) {
+                    char ab[64], db[64], cb[64];
+
+                    if (clk_net > 0)
+                        fprintf(fp, "always @(posedge %s) begin\n",
+                                em_cin(M, clk_net, cb, 64));
+                    else
+                        fprintf(fp, "always @(*) begin\n");
+
+                    if (we_net > 0) {
+                        char wb[64];
+                        fprintf(fp, "    if (%s)\n    ",
+                                em_cin(M, we_net, wb, 64));
+                    }
+
+                    fprintf(fp, "    %.*s[%s] <= %s;\n",
+                            (int)M->mems[i].name_len, mnam,
+                            em_cin(M, waddr, ab, 64),
+                            em_cin(M, wdata, db, 64));
+
+                    fprintf(fp, "end\n");
+                }
+            }
+
+            /* Read port is combinational — assign, not always.
+             * The DFF on the output handles the registration. */
+            {
+                uint32_t raddr = 0, rout = 0;
+                uint32_t ci3;
+                for (ci3 = 1; ci3 < M->n_cell; ci3++) {
+                    if (M->cells[ci3].type == RT_MEMRD &&
+                        M->cells[ci3].param == (int64_t)i) {
+                        raddr = M->cells[ci3].ins[0];
+                        rout = M->cells[ci3].out;
+                        break;
+                    }
+                }
+
+                if (raddr > 0 && rout > 0) {
+                    char ab2[64], ob[64];
+                    fprintf(fp, "assign %s = %.*s[%s];\n",
+                            em_cnet(M, rout, ob, 64),
+                            (int)M->mems[i].name_len, mnam,
+                            em_cin(M, raddr, ab2, 64));
+                }
+            }
+        }
+
+        fprintf(fp, "\n");
+    }
+
     /* ---- Cell instances ---- */
     for (i = 1; i < M->n_cell; i++) {
         const rt_cell_t *c = &M->cells[i];
@@ -403,6 +496,9 @@ em_vlog(const rt_mod_t *M, const lb_lib_t *lib,
         /* Skip CONST cells — inlined at consumers */
         if (ct == RT_CONST) continue;
 
+        /* Already handled above as reg arrays + always blocks */
+        if (ct == RT_MEMRD || ct == RT_MEMWR) continue;
+
         /* Look up mapped cell */
         if (!tbl[ct].valid) {
             fprintf(fp, "// UNMAPPED: %s w=%u\n",

src/rtl/tk_lower.c

@@ -48,6 +48,11 @@ typedef struct {
     #define LW_RDIR_MAX 512
     struct { uint32_t net, cur, cell; } rdir[LW_RDIR_MAX];
     uint32_t n_rdir;
+
+    /* Current write-enable condition for memory writes.
+     * Set by lw_ifmux when descending into an if body,
+     * cleared when leaving. 0 = unconditional. */
+    uint32_t mem_we;
 } lw_ctx_t;
 
 /* ---- Sequential redirect helpers ---- */
@@ -598,15 +603,27 @@ lw_asgn(lw_ctx_t *C, uint32_t nidx, int is_reg)
             uint32_t mw = C->M->mems[mi].data_w;
             uint32_t ci2;
 
-            /* Lower address and data */
+            /* Both sides of mem[addr] <= data need evaluating
+             * before we can build the write cell */
             anet = idx_n ? lw_expr(C, idx_n) : 0;
             dnet = lw_expr(C, rhs_n);
             if (anet == 0 || dnet == 0) return;
 
-            /* MEMWR: side-effecting, output is a dummy net */
+            /* If we're inside an if(we) block, the condition
+             * net rides along as a third input so the emitter
+             * can reconstruct the conditional write */
             onet = rt_anet(C->M, "mwr", 3, mw, 0, C->radix);
-            ins[0] = anet; ins[1] = dnet;
-            ci2 = rt_acell(C->M, RT_MEMWR, onet, ins, 2, mw);
+            {
+                uint32_t mins[3];
+                uint8_t mn = 2;
+                mins[0] = anet;
+                mins[1] = dnet;
+                if (C->mem_we > 0) {
+                    mins[2] = C->mem_we;
+                    mn = 3;
+                }
+                ci2 = rt_acell(C->M, RT_MEMWR, onet, mins, mn, mw);
+            }
             if (ci2 > 0 && ci2 < C->M->n_cell)
                 C->M->cells[ci2].param = (int64_t)mi;
             return;
@@ -925,14 +942,18 @@ lw_ifmux(lw_ctx_t *C, uint32_t nidx, int is_reg)
     }
 
 flat:
-    /* Pattern didn't match: lower all children flat */
+    /* Pattern didn't match: lower all children flat.
+     * Set mem_we so memory writes inside the if body
+     * pick up the condition as their write-enable. */
     {
-        uint32_t c = C->P->nodes[nidx].first_child;
-        KA_GUARD(g, 100);
-        while (c && g--) {
-            lw_stms(C, c, is_reg);
-            c = C->P->nodes[c].next_sib;
-        }
+        uint32_t saved_we = C->mem_we;
+        uint32_t cnet = cond_n ? lw_expr(C, cond_n) : 0;
+        if (cnet > 0)
+            C->mem_we = cnet;
+
+        if (then_n) lw_stms(C, then_n, is_reg);
+        C->mem_we = saved_we;
+        if (else_n) lw_stms(C, else_n, is_reg);
     }
 }