Build analyzers/schematic/signal_flow.py (clock-tree + reset + JTAG analyzer)

[RFingAdam]

Goal

Round out the schematic-aware analyzer suite (Phase 4b deferred this one). Track clock distribution, reset distribution, and JTAG/SWD pin accessibility from the schematic.

Acceptance criteria

• New src/mcp_pcb_emcopilot/analyzers/schematic/signal_flow.py module exposing analyze_signal_flow(schematic_components, schematic_nets) -> list[ReviewFinding].
• Clock-tree detection: identify clock sources (Y*/X* crystals, U* oscillators with values matching MHz/Hz), trace their net fan-out, flag stub-length > λ/20, flag fan-out > 4 unbuffered loads.
• Reset distribution: detect reset nets (*RESET*, *RST*, nRST), check for a single source (RC + supervisor / reset controller), flag multi-driver reset nets.
• JTAG / SWD accessibility: detect JTAG/SWD nets, verify presence of a test connector (J* with matching pins), flag designs without a debug header as HIGH severity for medical/automotive.
• Falls back to aggregate findings when pin-net mapping is absent (same pattern as other schematic analyzers).
• New pcb_analyze_signal_flow MCP tool; orchestrator wires it under sch_signal_flow and calls it when schematic_components is non-empty. Tool count 130 → 131.
• At least 8 unit tests covering: missing-clock, multi-driver reset, missing JTAG header, clean design, no-schematic-data path.

[RFingAdam]

Closed by PR #125 (commit ab37f5a). All CI checks (lint / typecheck / test 3.10-3.12) green.