Goal
Phase 4b shipped schematic-aware analyzers, but the test suite cannot exercise the real parsing paths because no schematic fixtures exist under tests/fixtures/. We need synthetic, minimal-but-valid fixtures for each supported schematic format so parser tests can run hermetically (no copyrighted reference designs).
Acceptance criteria
Goal
Phase 4b shipped schematic-aware analyzers, but the test suite cannot exercise the real parsing paths because no schematic fixtures exist under
tests/fixtures/. We need synthetic, minimal-but-valid fixtures for each supported schematic format so parser tests can run hermetically (no copyrighted reference designs).Acceptance criteria
tests/fixtures/sample_2sheet.kicad_sch— hierarchical schematic with at least: 2 sheets, 4 components (R/C/U), explicit (wire) (label) (junction),in_bom/on_boardproperties, MPN property.tests/fixtures/sample_schematic.pdf— single-page PDF with extractable text containing refdes + values.tests/fixtures/sample_netlist.NET— ORCAD PSTXNET-style netlist with at least 3 nets.tests/fixtures/sample.SchDoc— bytes-only stub recognised bydetect_formatas Altium (full OLE parsing is a separate issue).tests/conftest.pyexposes pytest fixtures for each.