v0.4.1: AltiumSchematicParser DNP/MPN/pin-net + ParsedSchematicData converter

Closes #121.

Production changes:
- AltiumSchematicParser._parse_fileheader: PIN (#2), SHEET_SYMBOL (#15),
  SHEET_ENTRY (#16), FILE_NAME (#33), WIRE (#27), JUNCTION (#29)
  record-type branches. NET_LABEL (#25) now also captures coordinates.
- Pin → net resolution: NetIdentifier wins, geometric fallback otherwise.
- AltiumSheetSymbol dataclass + sheet_symbols / child_sheets fields on
  AltiumSchematicData.
- altium_to_parsed_schematic() converter maps AltiumSchematicData →
  ParsedSchematicData with all DNP / MPN / Manufacturer / pins /
  child-sheet metadata preserved.
- SchematicParserFactory.parse() now converts Altium results so
  downstream analyzers see the unified ParsedSchematicData shape.

Refactor:
- KiCadSchematicParser._resolve_pin_nets extracted to
  parsers/_pin_net_geometric.py:resolve_pins_by_geometry(); both
  parsers call the shared helper.

Tests:
- Rewrite tests/test_altium_parameter_records.py — 17 integration cases
  exercise the real _parse_fileheader via synthetic FileHeader byte
  streams. Drops the duplicated _apply_params mirror that previously
  shadowed production logic. All existing tests stay green
  (1616 passed, 11 skipped).

Author: RFingAdam

CHANGELOG.md

@@ -5,6 +5,42 @@ All notable changes to **mcp-pcb-emcopilot** are documented here.
 The format follows [Keep a Changelog](https://keepachangelog.com/en/1.1.0/)
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
+## [0.4.1] — 2026-05-27
+
+### Added
+- **AltiumSchematicParser**: PIN (#2), SHEET_SYMBOL (#15), SHEET_ENTRY
+  (#16), FILE_NAME (#33), WIRE (#27), JUNCTION (#29) record-type
+  handling. NET_LABEL (#25) records now also capture coordinates for
+  geometric pin-net resolution.
+- **Pin → net resolution** for `.SchDoc` input: explicit `NetIdentifier`
+  parameter on a pin record wins; pins without one fall back to the
+  shared geometric resolver (label-anchor snap, same algorithm as
+  KiCad).
+- **Sheet-symbol hierarchy** — `AltiumSchematicData.sheet_symbols` and
+  `child_sheets` populated from SHEET_SYMBOL + FILE_NAME owner-index
+  linkage. Hierarchy now surfaces in `ParsedSchematicData.sheet_count`
+  and `properties['child_sheets']`.
+- **`altium_to_parsed_schematic()`** converter (in `altium_parser.py`):
+  maps `AltiumSchematicData` to the canonical `ParsedSchematicData`
+  shape downstream analyzers expect. `SchematicParserFactory.parse()`
+  wires the converter in so `.SchDoc` input flows through the same
+  analyzer surface as `.kicad_sch` — schematic-aware analyzers
+  (3-way cross-reference, signal-flow, schematic-layout validator)
+  stop running in degraded mode against Altium files.
+- **17 integration tests** in `test_altium_parameter_records.py` that
+  exercise the real `_parse_fileheader` against synthetic FileHeader
+  byte streams. The previous test scaffolding duplicated the
+  parameter-mapping logic inside the test file; that helper is gone.
+
+### Changed
+- `KiCadSchematicParser._resolve_pin_nets` extracted to
+  `parsers/_pin_net_geometric.py:resolve_pins_by_geometry()` so both
+  parsers share one implementation.
+
+### Closes
+- [#121](https://github.com/RFingAdam/mcp-pcb-emcopilot/issues/121) —
+  Extend AltiumSchematicParser for DNP / MPN / pin-net mapping.
+
 ## [0.4.0] — 2026-05-27
 
 ### Added

pyproject.toml

@@ -1,6 +1,6 @@
 [project]
 name = "mcp-pcb-emcopilot"
-version = "0.4.0"
+version = "0.4.1"
 description = "MCP server for PCB design review, EMC analysis, and signal integrity"
 readme = "README.md"
 license = "AGPL-3.0-or-later"

src/mcp_pcb_emcopilot/parsers/_pin_net_geometric.py

@@ -0,0 +1,109 @@
+"""Shared geometric pin → net resolver.
+
+Both KiCad and Altium schematic parsers face the same problem: a pin
+sits at a coordinate, a wire runs through it, and a net label
+anchored at a wire endpoint names the net. Neither tool exports an
+explicit netlist in the schematic file itself, so we infer
+connectivity from geometry.
+
+This module is the algorithm in one place so both parsers can call
+it without drifting.
+"""
+from __future__ import annotations
+
+from typing import Any, Iterable, Optional
+
+DEFAULT_SNAP_MM = 0.51
+
+
+def resolve_pins_by_geometry(
+    components: Iterable[Any],
+    wires: list[dict[str, Any]],
+    labels: list[dict[str, Any]],
+    junctions: list[dict[str, Any]],
+    nets: Optional[dict[str, Any]] = None,
+    snap_mm: float = DEFAULT_SNAP_MM,
+) -> None:
+    """Tag each component pin with the net of the nearest label.
+
+    Args:
+        components: iterable of objects with a ``pins`` list of dicts
+            (``ParsedComponent`` or ``AltiumComponent``). Each pin dict
+            should expose ``x_abs`` / ``y_abs`` (absolute coords in mm);
+            if absent, the component's own coordinate is used.
+        wires: list of ``{x1, y1, x2, y2}`` dicts in mm. Currently
+            unused in the snap-to-label heuristic but reserved so the
+            signature is stable as we add wire-walk net merging later.
+        labels: list of ``{name, x, y}`` dicts in mm.
+        junctions: list of ``{x, y}`` dicts in mm. Currently unused —
+            reserved for future cross-wire merging.
+        nets: optional mapping of ``{net_name -> net_object}`` where
+            ``net_object.pins`` is a list to append discovered pin
+            connections to. Pass ``None`` to skip the back-reference.
+        snap_mm: maximum distance from a pin to a label anchor for
+            the pin to be considered connected to that label's net.
+
+    Side effects:
+        - Each pin dict gets ``pin['net'] = label_name`` when within
+          tolerance.
+        - When ``nets`` is provided, the matching net object gets a
+          ``{'component': ref, 'pin_number': n}`` entry appended to
+          its ``pins`` list.
+    """
+    if not wires or not labels:
+        # Mark these as deliberately observed — the snap-to-label
+        # heuristic needs both to work, and the caller should not
+        # assume any pins were resolved if either is empty.
+        _ = wires, junctions
+        return
+
+    snap_sq = snap_mm ** 2
+
+    # Pre-compute label name → anchor coordinate. If multiple labels
+    # share a name (common for power nets like GND), the first wins;
+    # downstream geometry won't care because they share the same name.
+    label_anchors: dict[str, tuple[float, float]] = {}
+    for label in labels:
+        label_anchors.setdefault(label["name"], (label["x"], label["y"]))
+
+    for comp in components:
+        pins = getattr(comp, "pins", None)
+        if not pins:
+            continue
+        ref = getattr(comp, "reference", "")
+        comp_x = getattr(comp, "x_coord", None)
+        if comp_x is None:
+            comp_x = getattr(comp, "x_mm", 0.0)
+        comp_y = getattr(comp, "y_coord", None)
+        if comp_y is None:
+            comp_y = getattr(comp, "y_mm", 0.0)
+
+        for pin in pins:
+            # Skip pins that already have an explicit NetIdentifier
+            # — the caller resolved them ahead of the geometric pass.
+            if pin.get("net"):
+                continue
+
+            px = float(pin.get("x_abs", comp_x))
+            py = float(pin.get("y_abs", comp_y))
+            best_net: Optional[str] = None
+            best_d2 = snap_sq
+
+            for name, (lx, ly) in label_anchors.items():
+                d2 = (px - lx) ** 2 + (py - ly) ** 2
+                if d2 <= best_d2:
+                    best_d2 = d2
+                    best_net = name
+
+            if best_net is not None:
+                pin["net"] = best_net
+                if nets is not None:
+                    net = nets.get(best_net)
+                    if net is not None and hasattr(net, "pins"):
+                        net.pins.append({
+                            "component": ref,
+                            "pin_number": pin.get("pin_number", ""),
+                        })
+
+    # Junctions reserved for future cross-wire net merging.
+    _ = junctions