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AXI4-Lite Master / Slave UVM Lab

SystemVerilog UVM AXI4-Lite SVA

Runnable AXI4-Lite memory-mapped verification lab. It covers the five independent channels AW, W, B, AR and R with original public RTL examples.

Regression DUT UVM role Result
run_slave_dut.do AXI4-Lite register-bank slave Active UVM master driver with reference model AXI4L_SLAVE_DUT_PASS
run_master_dut.do Local-request to AXI4-Lite master Reactive UVM slave driver AXI4L_MASTER_DUT_PASS

Architecture

Slave DUT regression:
  random reads/writes -> UVM master driver -> AW/W/B/AR/R -> register-bank slave
                       -> reference model -> response checking

Master DUT regression:
  random local requests -> AXI4-Lite master DUT -> reactive UVM slave driver

axi4lite_checker.sv verifies that each VALID signal and its payload remain stable until the corresponding READY handshake occurs.

Scope

This repository implements AXI4-Lite, suitable for control/status registers and MMIO peripherals. Full AXI4 burst support requires additional work for ID, LEN, SIZE, BURST, boundary cases, ordering and outstanding transactions.

Run

PowerShell:

cd sim
powershell -ExecutionPolicy Bypass -File .\run_all.ps1

QuestaSim GUI:

cd sim
do run_slave_dut.do
do run_master_dut.do

The scripts default to C:/questasim64_10.2c.