ECHO-and-FIR-FILTER-implementation-on-Verilog-HDL/DE2_i2sound.qsf at master · MostafaOkasha/ECHO-and-FIR-FILTER-implementation-on-Verilog-HDL · GitHub

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# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors.  Please refer to the
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		DE2_i2sound_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "5.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:19:12  OCTOBER 26, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_G26 -to KEY0
set_location_assignment PIN_A6 -to I2C_SCLK
set_location_assignment PIN_B6 -to I2C_SDAT
set_location_assignment PIN_C5 -to AUD_ADCLRCK
set_location_assignment PIN_B5 -to AUD_ADCDAT
set_location_assignment PIN_A4 -to AUD_DACDAT
set_location_assignment PIN_A5 -to AUD_XCK
set_location_assignment PIN_B4 -to AUD_BCLK

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name TOP_LEVEL_ENTITY system

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP2C35F672C8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

set_global_assignment -name FMAX_REQUIREMENT "50 MHz" -section_id 50MHZ
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
set_location_assignment PIN_N26 -to SW[1]
set_location_assignment PIN_N25 -to SW[0]
set_location_assignment PIN_N2 -to CLOCK_50
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_instance_assignment -name CLOCK_SETTINGS 50MHZ -to CLOCK_50
set_location_assignment PIN_P25 -to SW[2]
set_location_assignment PIN_AE14 -to SW[3]
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name VERILOG_FILE CLOCK_500.v
set_global_assignment -name VERILOG_FILE i2c.v
set_global_assignment -name VERILOG_FILE keytr.v
set_global_assignment -name VERILOG_FILE parallel_to_serial.v
set_global_assignment -name VERILOG_FILE serial_to_parallel.v
set_global_assignment -name VERILOG_FILE system.v
set_global_assignment -name VERILOG_FILE dsp_subsystem.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VERILOG_FILE fir_filter.v
set_global_assignment -name VERILOG_FILE echo_machine.v
set_global_assignment -name QIP_FILE multiplier.qip
set_global_assignment -name QIP_FILE shiftregister.qip
set_global_assignment -name VERILOG_FILE potato.v
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top